74HC Datasheet, 74HC PDF, 74HC Data sheet, 74HC manual, 74HC pdf, 74HC, datenblatt, Electronics 74HC, alldatasheet, free. 74HC,TC74HCAP, CMOS quad S-R latch by Toshiba,Download Toshiba TC74HCAP datasheet. SN74LSA. (ACTIVE) Quad /S-/R latches. Datasheet ( KB). Description click to collapse contents. The ‘ offers 4 basic S\-R\ flip-flop latches in one.
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However is practically impossible to find good supply of it and even a datasheet. Backup question maybe deserving its own question: Any suggestion on how to implement this otherwise? Looks like an SR is my only choice here, but my brain is just a drop of the ocean.
EDIT — to clarify a few points in the design: The most complex part by design is planned to be the MCU. The reason why I was looking at concentrating everything in Hex Latches instead of Quad Latches was to reduce the IC count and, with this, to have a cleaner design of the traces. As far as possible I want to keep it digital and without any high frequency line anywhere or, better said, well confined in their own “realm”: MCU, comms module and voltage regulation sections.
On top of that, when I will get into power-optimization for the MCU I may end up having to choose between keeping the interrupts alive or saving power. I want to keep it flexible, both capability and power-usage wise and this requires balance. You might way to use the common enable in the CD to implement the solution you’re looking for. For this to work you need a pull-down resistor on every output. Most MCUs inputs can’t be configured with internal pull-downs, only with pull-ups.
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74HC279 Datasheet and 74HC279 manual
Thank you all for your help! Zio Stampella 8 3. Thanks for the reply. Yeah, looked at daasheet D and JK logic, but that would require providing clock and wouldn’t be an “unattended” design as I plan to implement. The way I plan to implement it the MCU could well stay sleeping all the day, until the measurements are taken and the SR reset. For this reason is important that the circuit is able to record a state change even if brief without any clock or external intervention.
Can’t yet wrap my head around applying a D or JK that way.
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Is there a reason why you have to use the fewest ICs? As has been said, you can make this function from more 74HCT-etc gates. While not the ideal for the approach here simple, cheap and reliable fatasheet, with only the MCU as “critical complexity”I believe that your comment may deserve an answer by itself for posterity.
But you all know how it works I think you need to re-evaluate how much power is required by “keeping the interrupts alive”. On processors such as the Atmel AVR that power is in the single microamp region – the clock doesn’t need to be running. Look for “Wake-up on pin ratasheet, not interrupt.
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You may be looking for this: Why does this work? If you look at the truth table of CD You can derive a similar deduction for CD Enric Blanco 4, 5 11 Hi, thanks for the reply!
The CD is indeed the one I have in the design now. The shortcoming is that I have 4 separate resets, while ideally I would need only one.
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While this is not a huge problem datasheft solve and still match my requirements, the resulting design is not as clear as it would be with a single Reset and the density is lower, requiring me to use more ICs. SNN simply has all of its reset inputs internally connected.
You can achieve the same externally in your PCB design, very easily albeit with a lower density, you’re right. Any way, take into account that the SNN has been obsolete for 25 years, its not a good idea to even consider that part for a new design.
Sourcing datssheet could be xatasheet troublesome. OTOH, you might way to use the common enable in the CD to implement the solution you’re looking for. Following up my previous comment: I have toyed briefly with the possibility to use the Enable line, but was not sure if it would have cleared the latched states.
Path-wise, the design difference wouldn’t look enormous, but would still be an improvement: I would spare the fixed via to the enable having datasheeg routed to the MCU and used to control the reset AND the enable itself and would have all the resets linked together in a clean way.
However the doubt stand. Is the enable line capable of effectively “resetting” the latches?
See line 1 of the question, it suggests the OP’s considered that. Their later comment says the MCU would be sleeping, before you posted your ‘answer’. Given the available info, this is probably the correct answer. A state change on the inputs would wake the MCU – whereupon it reads the inputs and then goes back to sleep. There’s a good chance that quiescent current added to the system by an extra logic IC would be greater than the current consumed by the MCU waking up and executing a handful of instructions.
I would disagree, but I may be missing the picture here. Historical anecdotes on my other uses for RS latches. Never say you are nobody! You matter to me!
Tony EE rocketscientist Comments like these are one of the many reasons for which I regret skipping all the theory in the electronic classes and being in the first line only when there was the risk to toast stuff. I would probably need to contemplate it for quite some time to fully grasp it. But I guess that the restrictions were far more I had a sync. No system this complex has shown up on this site. Sign up or log in Sign up using Google. Sign up using Facebook.